1. Field of the Invention
The present invention relates to an etching apparatus using a neutral beam, and more particularly, to a damage-free apparatus for etching a nanoscale semiconductor device using a neutral beam.
2. Description of the Related Art
As an increase in the integration density of semiconductor devices has been required, the design rule of integrated semiconductor circuits has been reduced. Thus, a critical dimension of 0.25 μm or less is needed. Ion enhanced etching tools, such as a high density plasma etcher and a reactive ion etcher are mainly used as etching tools for realizing nanoscale semiconductor devices. In such case, high density ions having energies of a few hundred eV bombard a semiconductor substrate or a specific material layer on the semiconductor substrate for anisotropic etching. The bombardment of such ions causes physical and electrical damages to the semiconductor substrate or the specific material layer.
Examples of physical damage are as follows. A substrate or a specific material layer having crystallinity is transformed into an amorphous layer. Also, a specific material layer, on which some incident ions are adsorbed or bombarded, of which partial components are only selectively desorbed therefrom to change chemical composition of a surface layer to be etched. Atomic bonds of the surface layer are changed into dangling bonds by this bombardment. Dangling bonds may result in electrical damage as well as physical damage. As electrical damage, there is gate dielectric charge-up or polysilicon notching due to photoresist charging. Besides this physical and electrical damages, there is also possible contamination by materials of a chamber or the contamination of a surface layer by a reactive gas such as the generation of C-F polymers caused by the use of a CF-based gas.
Physical and electrical damages due to the bombardment of ions reduces the reliability of nanoscale semiconductor devices and productivity. New apparatuses and methods for etching semiconductor devices are required to be developed in order to cope with the trend toward further increases in the integration density of semiconductor devices and reductions in design rule due to increased integration density.
D. B. Oakes et al. suggests a damage-free etching technique with a hyperthermal atomic beam in his thesis “Selective, Anisotropic and Damage-Free SiO2 Etching with a Hyperthermal Atomic Beam”. Japanese Takashi Yunogami et al. suggests a silicon oxide etching technique with a neutral beam or neutral radicals causes less damage in his thesis “Development of neutral-beam-assisted etcher” (J.Vac. Sci. Technol. A 13(3), May/June, 1995). M. J. Goeckner et al. suggests an etching technique with a hyperthermal neutral beam having no charges instead of plasma in his thesis “Reduction of Residual Charge in Surface-Neutralization-Based Beams” (1997 2nd International Symposium on Plasma Process-Induced Damage, May 13-14, Monterey, Calif.).
In the damage-free etching technique by D. B. Oakes et al., since ions do not exist, it is expected that electrical damages do not occur and contamination is low. However, scalability is difficult in that it is difficult to perform anisotropic etching on micro-devices, and etch rate is low. In the silicon etching technique by Takashi Yunogami et al., scalability is easy, but it is difficult to adjust the direction of the neutral beam and contamination possibility is high when extracting an ion beam. In the etching technique by M. J. Goeckner et al., scalability is possible and a high neutral beam flux can be obtained, but the direction of the neutral beam is not clear due to ion-electron recombination, ions are mixed, and contamination possibility is high when extracting ions.